1. Field of the Invention
The present invention relates to a substrate for a liquid crystal display device and the liquid crystal display device having the same, and more particularly to a substrate for a liquid crystal display device and a liquid crystal display device having the same which are suitably used in displaying an image of a high resolution such as a television image.
2. Related Background Art
A simple matrix type liquid crystal device having a pair of substrates, each having stripe electrodes, arranged to face each other with the electrode thereof crossing, is sufficient for displaying time or a simple image but there is a limit in time division drive and the number of pixels required increases in displaying an image which requires a high resolution and a high grade such as a television image and it is not possible to control it by the time division drive. Recently, an active matrix system has been developed to take place of the simple matrix system.
In an active matrix type liquid crystal drive device, a common electrode is provided on one of the substrates and a pixel electrode for each pixels is provided on the other substrate, and a thin film transistor (TFT) is arranged as a switching device for each pixel electrode. The TFT comprises two main electrodes called a source electrode and a drain electrode, and a control electrode called a gate electrode. In the active matrix system, one of the main electrodes is usually connected to a signal line, the other main electrode is connected to the pixel electrode, and the gate electrode is connected to a scan line. Which one of the main electrodes is to be used as the source electrode may vary depending on a type of the transistor and an applied voltage. In the present specification, an electrode closer to a display signal line is defined as a source electrode, and an electrode closer to the pixel electrode is defined as a drain electrode.
FIG. 1 shows an example of a TFT substrate of an active matrix type liquid crystal display device. In FIG. 1, numeral 2 denotes a scan line, numeral 3 denotes a signal line, numeral 4 denotes a pixel electrode, and numeral 10 denotes a TFT. As shown in FIG. 1, the scan lines 2 and the signal lines 3 are arranged in matrix and an operation of the TFT 10 provided for each pixel to control the application of a voltage to the pixel electrode 4 to attain a desired display.
FIGS. 2A to 2C show a TFT 10 and its periphery. In FIGS. 2A to 2C, numeral 1 denotes a gate electrode, numeral 6 denotes a semiconductor layer, numeral 7 denotes a source electrode, numeral 8 denotes a drain electrode, numerals 9-1 to 9-3 denote interlayer insulating layers, and numerals 2 to 4 denote the same as those of FIG. 1. FIG. 2B shows a B-B' sectional view of FIG. 2A and 2C shows a C-C' sectional view of FIG. 2A. In FIG. 2A and FIG. 2C, the interlayer insulating layer 9 is omitted for the purpose of simplification.
As shown in FIGS. 2A to 2C, the gate electrode 1 is formed on the semiconductor layer 6 which is formed on the insulating transparent substrate, through the interlayer insulating layer 9-1. The interlayer insulating layer 9-2 is formed thereon and a contact hole is formed in the interlayer insulating layer 9-2 to form the source electrode 7 and the drain electrode 8. Polycrystalline or amorphous Si, or single crystal Si is normally used as a material for the semiconductor layer 6, and poly-Si or a metal such as Al, Cr or Ta which may be easily filmed is used as a material for the gate electrode 1 and the scan line 2. The source electrode 7 and the signal line 3 are made of a metal such as Al, and the pixel electrode 4 is made of transparent indium tin oxide (ITO).
Since the required layers are arranged in overlapping or crossing manner in the periphery of the TFT, there is a step in a section as shown in FIG. 2B and FIG. 2C, and the layers coated on the step are easily broken.
Particularly in the gate electrode 1 extending from the scan signal line 2, a defect easily occurs in patterning by the semiconductor layer 6 in the step area, and this is one factor to reduce a yield of the TFT substrate. Further, as a pixel size increases, the length of the scan line increases and a resistance increases so that a sufficiently large pulse cannot be applied.